1. Field of the Invention
The present disclosure relates to liquid crystal display technology, and more particularly to an array substrate and the manufacturing method thereof.
2. Discussion of the Related Art
Conventional in-cell touch technology relates to dividing the common electrode (Com) within an active area (AA) to be small blocks, which operate as touch electrodes. Each of the touch electrodes connects to the Rx signal line of the touch chip (IC) to receive touch signals. Currently, Low Temperature Poly-silicon (LTPS) usually adopts the top gate of the thin film transistors (TFTs). To prevent the TFT within the AA area from leaking electricity, generally, a metallic layer is configured below the trench to block the light beams, that is, the so-called LSM layer.
The conventional InOcell design is shown in FIG. 1. A LSM layer 11 and a buffering layer 12 are formed on the glass substrate (not shown) in sequence. The polysilicon layer 132 is formed on the buffering layer 12. A doping process is applied to two lateral sides of the polysilicon layer 132 to form the doping area 132. Further, a heavy-doping area 133 is formed at one end of the polysilicon layer 132 facing away the polysilicon layer 132. A gate insulation layer 131 and a first metal layer 134 are formed on the polysilicon layer 132 in turn to form the gate. A first insulation layer 14 is formed on a second metal layer 135, and the second metal layer 135 is formed on the heavy-doping area 133 to form the source/drain (S/D). The second metal layer 135 passes through the first insulation layer 14. Further, an organic transparent layer 15 and a second insulation layer 141 are formed on the first insulation layer 14 in turn. A third metal layer 19 is formed on the second insulation layer 141 to operate as the Rx signal line. A third insulation layer 142, a touch electrode 16, a passivation layer 18, and a pixel electrode layer 17 are formed on the third metal layer 19 in turn. The pixel electrode layer 17 connects with the second metal layer 135 via a first through hole, and the touch electrode 16 connects with the third metal layer 19 via a second through hole.
It can be understood that a metal process has to be configured to form the Rx signal line during the manufacturing process of the array substrate. In addition, a through-hole process has to be configured in order to connect the Rx signal line and the touch electrode 16. The two manufacturing processes results in that the CMOS LTPS manufacturing process includes 14 masks. At the same time, in order to prevent the coupling capacitance (Cst) of the touch electrode and the Rx signal line from being too small, the thickness of the insulation layer between the third metal layer 19 and the touch electrode 16 cannot be too thin. Thus, the coupling capacitance between the touch electrode 16 and other Rx signal line cannot be too small.